Abstract:

Compared to the performance, cost, power and flexibility with the  hardware faulttolerant technique, the Software Implemented Hardware Fault Tolerance for COTS microprocessors hava many advantages. The fault tolerant compilation technology, which compiles at the compile time by automatically inserting instructions to achieve fault tolerance, which is easytoimplement, efficient and does not need to rewrite the source code. And  it reduces the burden for the programmer, and makes the  existing programs easytouse. Currently, it is the more active branches in the software fault tolerance research. This paper takes the GNU compiler GCC as a platform, gives an approach of the design and implementation for a faulttolerant compiler which combines with the existing faulttolerant algorithms.

Key words: fault tolerant compilation;GCC;redundance computing;software fault tolerance