Abstract:

This paper introduces a new structure for adders and branch modules with overflow processing. The particular overflow judgement signals are  needless,so it reduces the time overhead of the overflow processing.For the problem of control signals race on critical paths，two resolutions are given. Based on the view of mathematics，we reanalyse the relationship between control signals and input data，calculate the earlier arrived 0/1 signals firstly，and deferre the calculation time of the later arrived 0/1 signals.We make use of the previous stage’s operating period to raise the later arrived control signals，and so we succeede in the contention problem between the control signals. Finally we implement the design with the 0.13μm CMOS technology，and the maximum delay of the postlayout simulation is 590ps with 210ps off compared with the previous designs.It achieves the desired optimal purpose,and meets the calculation efficiency.

Key words: adder;overflow;overflow processing;control signal race