Abstract:

A new 5-stage pipelined architecture of floatingpoint fused multiplyadd (FMAC) unit is proposed and implemented. In this architecture, double precision or doublesingle precision floatingpoint multiply,multiplyadd and multiplysubtract operations are supported. The unit is implemented to RTL Code, and simulated and verified in Modelsim and NC Verilog. Further more, it is synthesized in the 65nm CMOS technology by Design Complier of Synopsys, and the frequency reaches 714.286MHz.In addition, compared with the  conventional lowdelay FMAC of paper ［3］ in the same environment, apart from 6.61 percent of area which could be acceptable is increased, 17.89 percent of delay and 25.08 percent of power is reduced.

Key words: floatingpoint multiply;floatingpoint fused multiplyadd (FMAC);SIMD;doublesingle precision floatingpoint