Abstract:

AES has its remarkable advantages in security, high performance, high efficiency, ease of use, flexibility, etc. As the demand of computation performance increases, researches on AES's FPGA implementation are paid more attention to. Based on the analysis of AES algorithm, a FPGA based fully pipelined AES model is proposed. In this model, the structure of the ae data block and wheel computation are modified in order to improve the performance of the AES hardcore. The implementation results on Altera EP4CE40F23C6 FPGA show that the proposed AES hardcore can run at 310 MHz with the computation throughput of 9.92 Gbps at the cost of 6413 LE and 80 M9K.       

Key words: AES;fully pipeline;computing acceleration;FPGA