Abstract:

Asynchronous circuit can resolve clockcaused problems in synchronous circuits, such as clock skew and high energy dissipation, attracting increasing attention. In order to implement full asynchronous communication among asynchronous modules on a chip and take advantage of asynchronous circuits in power consumption and performance, the paper designed an asynchronous bus PABLE (pipelinebased asynchronous bus for low energy), which is partially compatible with the synchronous AMBA AHB protocol and uses the asynchronous pipeline to improve the performance. Asynchronous arbitration circuit was designed, which can eliminate metastability. Finally, the desynchronization method was adopted to implement the PABLE. Results of the experiment show that, under the UMC 0.18um CMOS technology, for a single read or write operation, the read or write latency of the PABLE is lower than the synchronous bus in more than 60% cases and its average power consumption decreases by 41% compared with the synchronous bus.

Key words: asynchronous bus；pipeline；arbiter