• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

J4 ›› 2013, Vol. 35 ›› Issue (11): 175-181.

• 论文 • Previous Articles     Next Articles

An instruction level performance model of
parallel program based on hardware events           

LUO Hong-bing,WU Lin-ping   

  1. (High Performance Computing Center,Institute of Applied Physics and Computational Mathematics,Beijing 100094,China)
  • Received:2013-08-10 Revised:2013-10-18 Online:2013-11-25 Published:2013-11-25

Abstract:

The gap between peak performance of supercomputer and sustained performance of applications is becoming bigger and bigger, and many actual applications only reach 5%~10% of peak performance for supercomputer, or even less, therefore, performance problem is being gotten more and more concerns during parallel program development. A performance model based on hardware monitor events is proposed, which reveals relationship between performance and feature of program and processor. Based on the performance model, Euler and other programs are optimized on the Intel Xeon platform, and the execution time of hotspot modules such as gas1dapproxy is shortened by 12%~61%. The experiment results show that this model is helpful to optimize ILP performance of the scientific computing applications.

Key words: performance analysis;performance optimization;performance model;instruction level parallelism