Abstract:

DDR3 memory has become one of the mainstream applications in current servers and computer systems. Although many techniques such as dual reference voltage, dynamic ondie termination (ODT), flyby topology and writeleveling, have been adopt by DDR3 in order to improve signal integrity in a certain extent, it is still difficult to design and realize high data rate. Since DDR3 is a typical parallel bus structure, the simultaneous switching noise is couped with the original power noise, affecting the quality of data signals. Taking into account that the chip current is a dynamic changing and frequency related source, the paper proposes a new mixed simulation and design procedure based on target impedance and dynamic target impedance. The constant target impedance is adopted in presimulation, while the dynamic target impedance is used in postsimulation. The tradeoff between speed and accuracy of design optimization is realized, and simulation results prove the feasibility and efficiency of this method.

Key words: DDR3 DIMM；power integrity(PI)；dynamic target impedance