Abstract:

Abstract:The rapid development of Hash algorithm leads to two problems: one is the replacement of the old algorithms with the new ones when the products are upgraded, and the other is how to choose from different algorithms according to the security of the application environments. To solve the problems mentioned above, we design an SHA-1/SHA-256/SM3 IP multiplexing circuit, which makes use of the  loop unfolding technique and adds pipelines to each circuit. The circuit not only supports a variety of hash algorithms, but also features small area and high performance. The design is first implemented on a Xilinx Virtex-6 FPGA. It requires 776 slices and achieves a maximum throughput of 0.964Gbps. Then we also implement every circuit using the SMIC 0.13μm CMOS technology. The area of the circuit is 30.6k gates, which is reduced by 41.7% than that of the three circuits combined. Besides, the operating frequency of the circuit is 177.62 MHz, and the maximum throughput reaches 1.34Gbps.

Key words: Hash algorithm;SHA-1;SHA-256;SM3;IP multiplexing