[1] |
JIANG Jing-fei, HE Yuan-hong, XU Jin-wei, XU Shi-yao, QIAN Xi-fu.
NM-SpMM:A semi-structured sparse matrix multiplication algorithm for domestic heterogeneous vector processors
[J]. Computer Engineering & Science, 2024, 46(07): 1141-1150.
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[2] |
WEI Yi, YANG Zhi-jie, TIE Jun-bo, SHI Wei, ZHOU Li, WANG Yao, WANG Lei, XU Wei-xia.
A multistage dynamic branch predictor based on Hummingbird E203
[J]. Computer Engineering & Science, 2024, 46(05): 785-793.
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[3] |
ZHU Qi-jin, CHEN Xiao-wen, LU Jian-zhuang, .
Hardware design and FPGA implementation of a variable pipeline stage SM4 encryption and decryption algorithm
[J]. Computer Engineering & Science, 2024, 46(04): 606-614.
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[4] |
LIU Ru-lin, YANG Hui, LI Tao, L Gao-feng, SUN Zhi-gang.
Design and implementation of agile switching chip for equipment platform
[J]. Computer Engineering & Science, 2024, 46(02): 200-208.
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[5] |
WANG Rui-bo, WU Zhen-wei, ZHANG Wen-zhe, WU Hui-jun, ZHANG-YU Shu-qing, LU Kai.
Fine-grained memory access monitoring based on memory protection keys
[J]. Computer Engineering & Science, 2024, 46(01): 21-27.
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[6] |
WANG Cui-xia, HAN Lin, LIU Hao-hao.
Optimization of loop unrolling based on instruction Cache and register pressure
[J]. Computer Engineering & Science, 2022, 44(12): 2111-2119.
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[7] |
A test time optimization algorithm for multi-tower D SoCs based on partially pipelined test.
A test time optimization algorithm for multi-tower 3D SoCs based on partially pipelined test
[J]. Computer Engineering & Science, 2021, 43(11): 1934-1943.
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[8] |
WANG Xin, LIU Xiao-yan, ZHANG Kai-qi, WANG Xing, YAN Xin.
Design and implementation of a change event driven microservice composition platform
[J]. Computer Engineering & Science, 2021, 43(10): 1781-1788.
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[9] |
XUN Chang-qing, CHEN Zhao-yun, WEN Mei, SUN Hai-yan, MA Yi-min.
Compilation-oriented code analysis and optimization for Matrix DSP
[J]. Computer Engineering & Science, 2020, 42(10高性能专刊): 1791-1800.
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[10] |
SUN Tingting,HUANG Hao,WANG Jialun,WENG ChuliangSUN Tingting,HUANG Hao,WANG Jialun,WENG Chuliang.
A load balancing strategy on heterogeneous
CPU-GPU data analytic systems
[J]. Computer Engineering & Science, 2019, 41(03): 417-423.
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[11] |
XI Shengxin1,ZHANG Wenning2,ZHOU Qinglei1,SI Xueming3,LI Bin3.
High throughput implementation of
SHA512 on mimic computers
[J]. Computer Engineering & Science, 2018, 40(08): 1344-1350.
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[12] |
LIU Hui1,2,ZHAO Rongcai1,WANG Qi1.
A function-level compiler optimization parameter
selection method based on supervised learning model
[J]. Computer Engineering & Science, 2018, 40(06): 957-968.
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[13] |
ZHANG Kun,ZHENG Fang,XIE Xiang-hui.
A load-centric core pipeline design in
array many-core processors
[J]. Computer Engineering & Science, 2017, 39(12): 2167-2175.
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[14] |
TAN Yan-dan,YI Hui-zhan,ZHANG Peng.
Parallel iterative compilation
based on multi-core architecture
[J]. Computer Engineering & Science, 2017, 39(03): 436-442.
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[15] |
HAN Lin,LI Yingying.
Compiler curriculum construction
[J]. Computer Engineering & Science, 2016, 38(增刊): 286-289.
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