Abstract:

To maximize the performance, the frequency of the processor core becomes increasingly higher, and the design of the processor core gets much more complex. As a result, power issues become a challenge and need special care. Beside processlevel and circuitlevel low power technologies, adopting some strategies according to the features of modules during the RTL design can reduce power consumption. We analyze the power of an outoforder superscalar processor core and optimize the designs of register files and the reorder buffer based on the analysis. Evaluation results show that the area and power of the processor core decrease with no obvious performance penalty.

Key words: out-of-order, superscalar, performance, power