Abstract:

We analyze a high performance FPGA architecture of guided filtering for single image and find out that the mean filter of guided filtering has design defects. For this reason, we propose an integer FPGA architecture of guided filtering. Changing the sequence of data accumulation of the mean filter can reduce the use of memory on the FPGA. At the same time, we calculate the variance and transform coefficients of guided filtering by integer processing. Moreover, the size of image and filtering window can be changed flexibly via parameter adjustment. We implement the new architecture on the FPGA of Altera’s Cyclone, and experimental results show that the maximum error between the integer FPGA architecture’ processing result and the floating-point calculation result after rounding off is less than one. The new architecture greatly reduces the use of hardware resource and effectively improves the speed of data processing. When be implemented on the EP3C40F484C8, it is capable of processing images with dimension of 1024 by 1024 at the frame rate of 162 FPS, and can well meet the requirements of all kinds of real-time image processing.

Key words: guided filtering, FPGA, integer processing, mean filtering, image processing