Though silicon via (TSV) open/leakage defect reduces the reliability and yield of three-dimensional integrated circuits, so pre-bonding TSV tests are especially important. The existing charge and float, wait and sample (CAF-WAS) test method for  leakage defect test is superior to other methods such as ring oscillator, etc., however, it cannot test open defect. We propose a pseudo leak path thought to solve this problem. In addition, we redesign a waiting time generation circuit of to reduce the test time overhead. HSPICE simulation results show that the proposed method can accurately forecast the open defect and the scope of the leakage defect with only 25% test time of the existing method ［14］.