The RICE algorithm is widely used in the lossless compression system. Since it adopts the variable-length adaptive entropy coding, it’s necessary to make bit-wise judgment and analysis in the compressed stream when decoding. However, this makes it difficult to achieve high speed decompression. Existing RICE decoding implementation methods have unsatisfactory performance in decoding speed and versatility. Given the characteristics of the adaptive entropy coding in the RICE algorithm, we propose a parallel RICE decoding structure based on finite state machine (FSM) and look up table (LUT), which can perform 8-bit width  parallel decoding on the FPGA at the highest speed of 176 MB/s. And meanwhile, the decoding structure is suitable for the case where the coding parameter k is changeable, and hence it has strong versatility.