Processor pseudo-random test generators are important and necessary in processor research and development, which can generate large numbers of tests so as to cover the huge verification space. However, some of tests in the test set may become illegal and useless when the processor design changes, especially when instruction set or architecture changes, resulting in significant verification and maintenance costs. In order to tackle the problem, a hierarchical method based on models and libraries is proposed to create a processor pseudo-random test generator. Several techniques such as instruction set tree modeling, multidimensional memory address modeling and processor professional knowledge library modeling are used to solve the problem of how to efficiently reuse test sets in processor research and development. The practical application shows that this method can well adapt to the changes of processor design and enhance the usability and reusability of processor pseudo-random test generators. The reuse rate of test set can reach more than 95%, which can significantly shorten the verification cycle when the processor design is changed and upgraded.