[1] |
TANG Zhu, CHEN Baohai, WANG Jingyu, ZHU Qi.
OpenOCD debugging optimization for isomorphic asymmetric multi-core architecture
[J]. Computer Engineering & Science, 2025, 47(01): 45-55.
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[2] |
LIU Zhong, LI Cheng, TIAN Xi, LIU Sheng, DENG Rang-yu, QIAN Cheng-dong.
MVSim: A fast, scalable and accurate architecture simulator for VLIW multi-core vector processors
[J]. Computer Engineering & Science, 2024, 46(02): 191-199.
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[3] |
LUO Li, ZHOU Hong-wei, ZHOU Li, PAN Guo-teng, ZHOU Hai-liang, LIU Bin.
QoS design and verification of direct connection interface for multi-core processors
[J]. Computer Engineering & Science, 2021, 43(04): 620-627.
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[4] |
MA Yan-yan1,YANG Zhi-bin1,2,JIANG Guo-hua1.
An automatic transformation method
from SysML model to AADL model
[J]. Computer Engineering & Science, 2020, 42(03): 456-466.
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[5] |
ZHANG Xiang-yu,SHI Hui-li.
A multi-core DSP development
platform based on Ethernet and PCIe
[J]. Computer Engineering & Science, 2019, 41(10): 1731-1737.
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[6] |
CHEN Qian,LIU Yun,GAO Yuying.
A parallel dynamic bit vector based frequent
closed sequence pattern mining algorithm
[J]. Computer Engineering & Science, 2018, 40(10): 1717-1725.
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[7] |
LI Jin1,LUO Xin-jie2,HU Xiao1,CHEN Yue-yue1.
OpenCV parallel optimization on TI 6678 DSP
[J]. Computer Engineering & Science, 2018, 40(05): 780-786.
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[8] |
YANG Sheng-zhe,YU Jun-qing,TANG Jiu-fei.
Dynamic task scheduling and optimization of data flow program
[J]. Computer Engineering & Science, 2017, 39(07): 1201-1210.
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[9] |
HU Jun,CHEN Song,WANG Ming-ming.
A transformation method for AltaRica3.0
to Promela and its verification
[J]. Computer Engineering & Science, 2017, 39(04): 708-716.
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[10] |
DU Qi,JIANG Hao,LI Kuan,PENG Lin,YANG Can-qun.
QTRSM on ARMv8 64-bit multi-core processor
[J]. Computer Engineering & Science, 2017, 39(03): 451-457.
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[11] |
WANG Jun,LIU Lei,ZHANG Long,LI Sikun.
Multi-core transaction level modeling and
multi-view co-verification environment
[J]. J4, 2014, 36(05): 821-827.
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[12] |
CHEN Fangyuan1,DING Yajun1,ZHANG Dongsong2,WU Fei3, REN Xiujiang1.
Research of realtime multi-core architecture for WCET analysis
[J]. J4, 2014, 36(03): 393-398.
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[13] |
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[J]. J4, 2008, 30(9): 116-118.
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[14] |
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[J]. J4, 2008, 30(1): 119-122.
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[15] |
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[J]. J4, 2006, 28(12): 114-117.
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