• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

Computer Engineering & Science

Previous Articles     Next Articles

A hardware acceleration method for the normalized
product correlation algorithm and its FPGA implementation

LI Hong-jun1,2,GUO Yang1,JIA Run2   

  1. (1.School of Computer,National University of Defense Technology,Changsha 410073;
    2.Tianjin Jinhang Institute of Computing Technology,Tianjin 300141,China)
  • Received:2019-03-01 Revised:2019-06-13 Online:2019-11-25 Published:2019-11-25

Abstract:

With the trend that cruise missiles aim at high efficient attack and intelligent enhancement, only using DSP software to process images cannot satisfy the higher real-time requirements for terrain matching and target recognition. Therefore, according to the advantage of FPGA implementation on computation accelerating, this paper proposes a simplification method for the normalized product correlation algorithm formula, which has the characteristics of high precision and high speed, and designs the product correlation’s hardware acceleration unit and multi-channel parallel computing architecture. FPGA implementation verifies that the proposal can satisfy the real-time requirements for terrain matching and target recognition of the new generation of cruise missiles.
 

Key words: normalized product correlation, parallel computing, hardware acceleration