Field Programmable Gate Array (FPGA) has broad prospects in computer vision applications. However, limited memory resources of FPGA are difficult to meet the performance, size and power requirements of the application scenarios. To solve this problem, this paper studies the resource allocation of on-chip memory, designs a partition balancing algorithm to minimize resource usage and power consumption, and implements it on the platform. The experimental results show that, compared with the commercial FPGA's advanced synthesis tools, the proposed algorithm improves the utilization rate by 60% and reduces the dynamic power consumption by up to 70%. In the experiment of the advanced algorithm MeanShift tracking, the experimental data shows that the partition balancing algorithm can reduce the total power consumption by up to 30% without affecting the key performance.

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