Abstract: In order to simplify the complexity of network on chip with medium scale and improve the efficiency of the networks, a bi-ring network on chip based on deflection routing is proposed. Its collision resolving mechanism is studied, and a simple and efficient routing algorithm is given. The bi-ring network on chip is implemented by Hardware Description Language (HDL) and its cycle-accurate simulation is constructed. The experimental results show that the bi-ring network has the similar performance with the YARC on-chip network with 100% throughput, but has far less hardware cost.

Key words: network on chip, deflection routing, ring network, network performance, hardware cost