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HAN Jin, WU Zewei.
Design of AES_ll coprocessor based on RISC-V
[J]. Computer Engineering & Science, 2026, 48(1): 79-88.
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ZHANG Yu er, XI Yuhao, LIU Peng.
Designing and optimizing RISC-V instruction set functionality based on multi-operand acceleration
[J]. Computer Engineering & Science, 2025, 47(6): 968-975.
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ZHANG Weiwei, CHEN Hu.
A multi-threaded interrupt-free RISC-V processor for low-latency acceleration component control
[J]. Computer Engineering & Science, 2025, 47(5): 787-796.
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SHEN Jinshang, ZHANG Qingshun, SONG Tierui.
Implementation of high-speed AES based on FPGA and improvement of MixColumn
[J]. Computer Engineering & Science, 2025, 47(4): 612-620.
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LIAN Zihan, HE Weifeng.
High-performance processor design based on dynamic timing slack exploitation
[J]. Computer Engineering & Science, 2025, 47(2): 219-227.
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HU Jintao, XU Xuezheng, YANG Deheng, HUANG Anwen, KOU Guang, LI Qiong.
An efficient method for RISC-V memory consistency testing based on loop unrolling
[J]. Computer Engineering & Science, 2025, 47(11): 1932-1944.
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WANG Haonan, WANG Zhen.
New attack modes and protection measures for configurable approximate adder
[J]. Computer Engineering & Science, 2025, 47(10): 1756-1766.
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WANG Jie, FU Dan-yang, .
ROB compression method based on RISC-V superscalar processor
[J]. Computer Engineering & Science, 2024, 46(7): 1185-1192.
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WEI Yi, YANG Zhi-jie, TIE Jun-bo, SHI Wei, ZHOU Li, WANG Yao, WANG Lei, XU Wei-xia.
A multistage dynamic branch predictor based on Hummingbird E203
[J]. Computer Engineering & Science, 2024, 46(5): 785-793.
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LI Fei, GUO Shao-zhong, ZHOU Bei, SONG Guang-hui, HAO Jiang-wei, XU Jin-chen.
Performance optimization of RISC-V basic math library
[J]. Computer Engineering & Science, 2023, 45(9): 1532-1543.
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SUN Cai-xia, SUI Bing-cai, DENG Quan, ZHENG Zhong, NI Xiao-qiang, WANG Yong-wen.
A hybrid ISA processor compatible with RISC-V at application level
[J]. Computer Engineering & Science, 2023, 45(8): 1347-1353.
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ZHOU Li, ZHAO Zhi-qiao, PAN Guo-teng, TIE Jun-bo, ZHAO Wang.
RISC-V based design of graph convolutional neural network accelerator
[J]. Computer Engineering & Science, 2023, 45(12): 2113-2120.
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CHEN Zi-yu, HE Jun, GUO Xiang-yu.
Implementation of cryptographic instructions for general purpose processors
[J]. Computer Engineering & Science, 2022, 44(7): 1162-1170.
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LU Song, JIANG Ju-ping, REN Hui-feng.
Quick customization for RISC-V processor based on FPGA
[J]. Computer Engineering & Science, 2022, 44(10): 1747-1752.
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GU Yue, ZHAO Yin-liang.
Implementation and optimization of sparse matrix vector multiplication based on RISC-V vector instruction
[J]. Computer Engineering & Science, 2022, 44(1): 1-8.
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