Abstract: Mapping convolutions to matrix multiplications is an efficient implementation on FPGA. However, the existing conversion methods cannot be dynamically adjusted according to different convolution parameters, which limits the parallelism of convolution calculation. This paper proposes a novel dynamic residue processing mapping model. The mapping model contains three sub-models: feature mapping model, weight mapping model, and output mapping model. The feature mapping model converts features into a feature matrix, and the weight mapping model converts weights into a weight matrix. The feature matrix and the weight matrix obtain convolution calculation results by multiply-and- accumulate array, and the convolution calculation results are stored in the memory by the output mapping model. In the process of convolution calculation, the number of output channels of the convolution is usually not an integer multiple of the number of rows of the multiply-and-accumulate array. The three sub-mapping models will dynamically adjust the mapping method according to the remaining number to increase the utilization of the multiply-accumulated array. Experiments show that using the dynamic remainder processing mapping model can increase the multiple of parallelism up to the size of the convolution kernel and achieve higher actual throughput and energy efficiency.

Key words: convolution, matrix multiplication, FPGA, dynamic remainder processing