Abstract: To make up for the shortcomings of the traditional video image splitter such as weak anti-interference ability, low frame rate, and complex design, Xilinx Zynq XC7Z035 FPGA heterogeneous platform is selected and integrated with SDI technology. The high-definition digital serial decoding chip TW6874 is used to synchronously collect 4 digital video images, and output BT.1120 data to FPGA, in order to realize the separate display of 4 channels of video. In order to meet the resolution and frame rate requirements of video images, pixel resampling of video image data is first performed. Secondly, AXI4-Stream Data FIFO is used for line input buffering, which is flexible in processing data and easy to expand, which provides a basis for further integration of algorithms. AXI4-Stream Data FIFO generates s_axi_s2mm_tlast signal for each line of 960 data and handshake with AXI DMA, buffers the data in DDR3 SDRAM, and buffers the next buffer address after 540 lines. AXI DMA has 3 video images per channel buffer, thus completing the three-buffer design, to ensure that the video image is not torn. Finally, the cached data is output to the SMPTE SDI IP core for display. The experimental results show that the system realizes the 4-channel SDI video image segmentation, the system resource utilization rate is low, the video image frame rate is high, the layer is obvious, and no tearing and distortion occurs.

Key words: Zynq, SDI, BT.1120, AXI DMA, line buffer, DDR3 SDRAM, three caches