Abstract: The arctangent operation is one of the common operations in applications such as scientific computing, digital signal processing, and graph processing. Based on the piecewise algorithm, a single-precision floating-point arctangent arithmetic unit conforming to the IEEE-754 standard is designed for a certain type of DSP chip. To achieve the accuracy required by the design, all errors in the calculation process are analyzed and limited. To make the monotonicity of the output result consistent with the original function, a design method that can guarantee the monotonicity of the algorithm is proposed. To reduce hardware cost, a two-level hierarchical segmentation method is used, and the signal bit width design and optimization based on circuit static and dynamic analysis are realized. The FPGA-based simulation results show that the hardware cost of the arctangent operator is relatively small, the error between the output and the standard result is less than 1 ulp, and the operator has excellent output monotonicity.

Key words: arctangent, error analysis, hierarchical segmentation, bit width optimization, monotonicity