[1] |
JIANG Jing-fei, HE Yuan-hong, XU Jin-wei, XU Shi-yao, QIAN Xi-fu.
NM-SpMM:A semi-structured sparse matrix multiplication algorithm for domestic heterogeneous vector processors
[J]. Computer Engineering & Science, 2024, 46(07): 1141-1150.
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[2] |
WANG Jie, FU Dan-yang, .
ROB compression method based on RISC-V superscalar processor
[J]. Computer Engineering & Science, 2024, 46(07): 1185-1192.
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[3] |
SHI Yang, CHEN Zhao-yun, SUN Hai-yan, WANG Yao-hua, WEN Mei, HU Xiao.
Design of independent software stack of FT-Matrix DSP
[J]. Computer Engineering & Science, 2024, 46(06): 968-976.
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[4] |
LIU Zhong, LI Cheng, TIAN Xi, LIU Sheng, DENG Rang-yu, QIAN Cheng-dong.
MVSim: A fast, scalable and accurate architecture simulator for VLIW multi-core vector processors
[J]. Computer Engineering & Science, 2024, 46(02): 191-199.
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[5] |
MA Ke-fan, LI Bao-feng, ZHOU Yue-jin, WU Yuan-yuan, YU Yong-lan, DUO Rui-hua.
Design and implementation of a baseboard management controller on ZYNQ chip
[J]. Computer Engineering & Science, 2024, 46(02): 217-223.
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[6] |
ZHOU Li, ZHAO Zhi-qiao, PAN Guo-teng, TIE Jun-bo, ZHAO Wang.
RISC-V based design of graph convolutional neural network accelerator
[J]. Computer Engineering & Science, 2023, 45(12): 2113-2120.
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[7] |
ZHENG Kang, LI Chen, CHEN Hai-yan, LIU Sheng, FANG Liang.
Design and optimization of scalar memory access unit in VLIW DSPs
[J]. Computer Engineering & Science, 2023, 45(11): 1929-1940.
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[8] |
ZHU Wen-long, JIANG Jia-zhi, HUANG Dan, XIAO Nong.
ParM: A heterogeneous programming model for domestic processors
[J]. Computer Engineering & Science, 2023, 45(09): 1521-1531.
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[9] |
LI Fei, GUO Shao-zhong, ZHOU Bei, SONG Guang-hui, HAO Jiang-wei, XU Jin-chen.
Performance optimization of RISC-V basic math library
[J]. Computer Engineering & Science, 2023, 45(09): 1532-1543.
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[10] |
ZHOU Cong, TAO Jing, ZHAO Bao-kang, LI An-yi.
A dual search strategy for modifying the longest matching rule in domain name service
[J]. Computer Engineering & Science, 2023, 45(09): 1572-1577.
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[11] |
SUN Cai-xia, SUI Bing-cai, DENG Quan, ZHENG Zhong, NI Xiao-qiang, WANG Yong-wen.
A hybrid ISA processor compatible with RISC-V at application level
[J]. Computer Engineering & Science, 2023, 45(08): 1347-1353.
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[12] |
ZHU Ying, TIAN Zeng, CHEN Ye, JIANG Yi-fei, LI Yan-zhe, LIU Xiao-qiang.
Design of an embedded processor with high reliability
[J]. Computer Engineering & Science, 2023, 45(03): 390-397.
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[13] |
CUI Xin-yue, JIANG Lin, YANG Kun, HUI Chao, HU Chuan-zhan, ZHAO Jing.
A dynamic self-reconfigurable implementation method of HEVC intra prediction algorithm
[J]. Computer Engineering & Science, 2022, 44(12): 2120-2127.
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[14] |
ZANG Zhao-hu, LI Chen, WANG Yao-hua, CHEN Xiao-wen, GUO Yang .
A hierarchical hardware barrier synchronization design for many-core processors
[J]. Computer Engineering & Science, 2022, 44(11): 1901-1908.
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[15] |
GUO Pan-pan, CHEN Meng-xue, LIANG Zu-da, MA Xiao-chang, XU Bang-jian.
Optimization of dot product algorithms on FT-M7002
[J]. Computer Engineering & Science, 2022, 44(11): 1909-1917.
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