Abstract: The implementation of intra-frame prediction algorithm in High Efficiency Video Coding (HEVC) on dedicated hardware cannot meet the requirements of flexible switching between various application scenarios such as HD and mobile video, resulting in poor coding performance and low utilization of hardware resources. To solve this problem, a new implementation method of intra-frame prediction algorithm on the reconfigurable array processor is proposed. The method is based on the state monitoring mechanism. When the idle processing unit is detected, a new execution task is delivered, and the flexible switching between different mapping schemes is realized according to the execution state of the processing unit, so as to achieve the dynamic self-reconstruction of the algorithm execution process. The experimental results show that, compared with the implementation of the intra prediction algorithm on the dedicated processor, the hardware resources are reduced by 33.6% and the number of clock cycles is reduced by 16.2%. Compared with the test results of HM16.7 official software, the average image quality is improved.

Key words: dynamic self-reconfiguration, array processor, state monitor, high efficiency video coding (HEVC), intra-frame prediction ,