Abstract: In the development process of SoC, how to efficiently and accurately perform functional verification and performance analysis is an urgent problem to be solved. Aiming at the current limited monitoring means of Network-on-Chip protocols on FPGA prototype platforms, this paper proposes an efficient monitoring and analysis method with hardware-software mixture for CHI  protocols. By connecting C code through the DPI of SystemVerilog, the synthesizable hardware part provides a shared function body, while the non-synthesizable software part captures CHI messages in the SoC under test from various channels of the Network-on-Chip protocol through the shared function body for offline storage or online inspection. Experimental results show that this method has the advantages of low hardware resource occupation and high reusability. The offline mode has little impact on simulation speed, while the online mode can detect problems while the SoC under test is running, enabling efficient monitoring of CHI protocol mes- sages on the prototype platform and effectively accelerating the localization and performance analysis of SoC problems.

Key words: coherent hub interface (CHI) protocol, FPGA, verification of chip, hardware-software mixture ,