Abstract: In recent years, open-source RISC-V microprocessors represented by Hummingbird E203 have received widespread attention and application in both academia and industry due to their low power consumption and good performance. To improve the performance of microprocessors and reduce pipeline stalls caused by branch instructions, branch prediction technology has become one of the important techniques widely used in modern microprocessors. However, the branch predictor currently used in the Hummingbird E203 is a lightweight static branch predictor, facing the challenge of low branch prediction accuracy. Since using a dynamic branch predictor with higher prediction accuracy can further reduce the overhead caused by mispredictions leading to redirecting fetching, various implementations of dynamic branch predictors have been explored based on the original microarchitecture to improve branch prediction accuracy while considering resource overhead. Experimental results show that among various dynamic branch predictors, the one achieving the best results is the adaptive dynamic branch predictor combining static branch prediction with Branch History Register (BHR). On the Dhrystone benchmark program, its branch prediction accuracy can be increased from the original 84.6% to 94.8%, and the score from 1.296 463 to 1.314 418. On the Coremark benchmark program, its branch prediction accuracy can be increased from the original 67% to 78.7%, and the score from 2.120 000   to 2.138 008.

Key words: dynamic branch prediction, Hummingbird E203, RISC-V, pipeline, microarchitecture