[1] |
HUANG Zhi-rui, JIA Xin-ru, , ZHU Hao-zhe, , CHEN Chi-xiao, .
A low-power keyword spotting system with SRAM buffer and computing-in-memory
[J]. Computer Engineering & Science, 2024, 46(08): 1331-1339.
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[2] |
JIANG Jing-fei, HE Yuan-hong, XU Jin-wei, XU Shi-yao, QIAN Xi-fu.
NM-SpMM:A semi-structured sparse matrix multiplication algorithm for domestic heterogeneous vector processors
[J]. Computer Engineering & Science, 2024, 46(07): 1141-1150.
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[3] |
GUI Dan, YU Zong-jie.
An automatic calculation system of arbitrary waveform THD for small signal amplification circuit
[J]. Computer Engineering & Science, 2022, 44(07): 1199-1206.
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[4] |
ZHUANG He-lin, YANG Huo-gen, XIA Xiao-yun, LIAO Wei-zhi.
Artificial bee colony algorithm for matrix multiplication problem
[J]. Computer Engineering & Science, 2021, 43(12): 2131-2138.
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[5] |
LI Chuang, LIU Zong-lin, LIU Sheng, LI Yong, XU Xue-gang, XIA Yi-min.
A survey of fast convolution algorithms
[J]. Computer Engineering & Science, 2021, 43(10): 1711-1719.
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[6] |
ZHAO Xiao-qiang, JIANG Jing-fei, XU Jin-wei, DOU Yong.
A dynamic remainder processing mapping model for convolutional neural network accelerator on FPGA
[J]. Computer Engineering & Science, 2021, 43(09): 1521-1528.
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[7] |
JIA Xun, QIAN Lei, YUAN Hao, ZHANG Kun, WU Dong.
Design of BLAS level3 computation on a matrix multiplication coprocessor
[J]. Computer Engineering & Science, 2020, 42(11): 1913-1921.
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[8] |
WANG Ji-jun,HAO Zi-yu,LI Hong-liang.
3D-MMA:Matrix multiplication accelerator
architecture based on 3D integrated circuits
[J]. Computer Engineering & Science, 2019, 41(12): 2110-2118.
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[9] |
JIA Xun,WU Guiming,QIAN Lei,XIE Xianghui,WU Dong.
An efficient solver for large-scale triangular linear equations
[J]. Computer Engineering & Science, 2019, 41(02): 240-245.
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[10] |
GAN Xin-biao1,2,SUN Liao-yuan3,LIU Jie1,XIONG Cheng-wei1,HUANG Jia-kun1.
Orchestrating HPL between CPU and China accelerator
[J]. Computer Engineering & Science, 2018, 40(01): 10-14.
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[11] |
ZHU Min,TANG Bo,ZHAO Juan,ZOU Dan,LI Jincai.
Distributed heterogeneous parallel Boolean
matrix multiplication and its performance optimization
[J]. Computer Engineering & Science, 2017, 39(04): 634-640.
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[12] |
SHEN Jun zhong,XIAO Tao,QIAO Yu ran,YANG Qian ming,WEN Mei.
A matrix multiplication accelerator design for optimization blocking strategy
[J]. Computer Engineering & Science, 2016, 38(09): 1748-1754.
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[13] |
WANG Min,CAO Qingjing,YUN Weiguo,ZHOU Junni.
Application of an improved MFCC algorithm
in the identification of individual crested ibis
[J]. J4, 2016, 38(05): 1052-1056.
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[14] |
ZHOU Leitao1,2,TAO Yaodong2,LIU Sheng1,2,LI Suo3.
Research on Systolic multiplication technology based on FPGA
[J]. J4, 2015, 37(09): 1632-1636.
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[15] |
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[J]. J4, 2008, 30(7): 98-99.
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