Abstract: With the significant increase in communication bandwidth, low jitter, as a crucial indicator of signal transmission quality in multi-scenario applications, has become an important research direction in signal integrity. The 56 Gbaud Retimer chip serves as the key component in optical interconnection data transmission for high-performance computers, and its jitter performance also restricts the overall performance of the optical module in high-performance computers. To address the challenge of low jitter performance in traditional high-speed Retimer chips, a low-jitter Retimer circuit with a data rate exce- eding 100 Gbps is proposed for the first time. This Retimer circuit, based on the CDR+PLL architecture, is integrated into a fiber optic repeater, featuring equalization and full-rate retiming functions. By adopting a jitter elimination filter circuit, it achieves excellent output data jitter performance under high-noise input signals, providing technical support for solving the issue of high output data jitter caused by direct sampling and forwarding in traditional Retimers. The design of the low-jitter Retimer circuit based on the CDR+PLL architecture was completed using TSMC 28 nm CMOS technology. Simulation results show that when the input is 112 Gbps PAM4, the output data jitter of the Retimer is 741 fs, representing a 31.4% reduction compared to traditional Retimer structures. 

Key words: Retimer circuit, clock and data recovery (CDR), phase locked loop (PLL), low jitter