Abstract: In recent years, emerging applications in fields such as autonomous driving, medical instruments, and smart homes have placed higher demands on the real-time performance and data throughput capabilities of DSP processors. The use of multi-level cache structures in DSPs introduces latency uncertainties due to processes such as cache misses and coherency maintenance. Aiming at allevi- ating the performance degradation caused by long delay access, the method of combining miss status holding registers and victim buffer into one structure is proposed. This structure allocates its item function flexibly at runtime to improve buffer utilization. Aiming at the low synchronization efficiency of coherency maintenance information between L1  Cache and L2  Cache, this paper proposes to use the continuity between invalid addresses to synchronize invalid information to the snoop filter without blocking. The test results show that the performance of the producer-consumer scenario program with many dirty data updates is improved by 19.91%, and the synchronization time of 32 lines of invalid information decreased from 61 cycles to 16 cycles.

Key words: digital signal processer (DSP), L2 Cache, pipeline, coherency