| [1] |
HE Xingyang1, 2, ZHOU Hongwei1, 2, ZHOU Yuxuan1, 2, SUN Yubo3, LI Mengjin1, 2.
Research on multi-protocol support technology and standardization in Chiplet interconnection interface
[J]. Computer Engineering & Science, 2025, 47(9): 1521-1534.
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| [2] |
SUN Yubo1, ZHOU Hongwei2, 3, SUN Xingyu2, 3, HE Xingyang2, 3, SONG Zhaoyang2, 3, CHEN Zhiqiang2, 3.
Research on Retimer structure and key technologies for Chiplet interconnection
[J]. Computer Engineering & Science, 2025, 47(8): 1381-1390.
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| [3] |
HONG Wentao, WU Lizhou, ZHANG Jintao, MENG Fanfeng, OU Yang, WANG Zicong, XIAO Nong .
A survey of memory pool systems based on emerging memory-semantic interconnect protocols
[J]. Computer Engineering & Science, 2025, 47(4): 601-611.
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| [4] |
XIONG Guo-jie, ZHANG Jin-ming, HE Guang-hui.
Design and implementation of an efficient transmission protocol for Chiplet interconnection
[J]. Computer Engineering & Science, 2023, 45(8): 1339-1346.
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| [5] |
SHI De-jun, LI Hong-liang, HU Shu-kai .
A Clos network based high-radix router structure
[J]. Computer Engineering & Science, 2023, 45(12): 2099-2112.
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| [6] |
CAO Ji-jun.
Review of reconfigurable optical interconnection network architecture for HPC and DC
[J]. Computer Engineering & Science, 2022, 44(6): 951-963.
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| [7] |
LIANG Chong-shan, DAI Yi, XU Wei-xia.
A super high-radix router based on Chiplet integration technology
[J]. Computer Engineering & Science, 2022, 44(2): 207-213.
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| [8] |
WANG Xin, LIN Fang, LIU Yi, QIAN De-pei.
A large-scale Infiniband interconnection network simulation system based on OMNet++
[J]. Computer Engineering & Science, 2021, 43(5): 792-798.
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| [9] |
SUN Xiao-le, QIAN Ya-long, QI Xin-xin, ZHANG Yun-fang, CHEN Juan, YUAN Yuan, DONG Yong.
Analysis and optimization of power consumption characteristics of Network-on-Chip
[J]. Computer Engineering & Science, 2020, 42(7): 1141-1150.
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| [10] |
WANG Xi1,2,ZHANG Shu-kui2.
Diagnosability and a new diagnosis algorithm
of Cross-cube in fault situation
[J]. Computer Engineering & Science, 2020, 42(4): 588-595.
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| [11] |
WANG Chao, CAO Jijun, LUO Zhang, LAI Mingche, XU Weixia.
Research and implementation of lowlatency forward error correction coding for HPC interconnection network
[J]. Computer Engineering & Science, 2020, 42(11): 1965-1972.
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| [12] |
XIE Min, ZHANG Wei, ZHOU En-qiang, DONG Yong.
Implementation of scalable communication framework on TH-express interconnection
[J]. Computer Engineering & Science, 2020, 42(10高性能专刊): 1720-1729.
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| [13] |
JIANG Ju-ping, DONG De-zun, TANG Hong, QI Xing-yun, CHANG Jun-sheng, PANG Zheng-bin.
Performance evaluation of large-scale HPC interconnection network topologies
[J]. Computer Engineering & Science, 2020, 42(10高性能专刊): 1730-1736.
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| [14] |
LU Ping-jing, LAI Ming-che, WANG Bo-chao, CHANG Jun-sheng.
A fusion network architecture for computing and interconnection
[J]. Computer Engineering & Science, 2020, 42(10高性能专刊): 1737-1741.
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| [15] |
GUO Xintong,LEI Yuanwu,GUO Yang.
Design and implementation of dual-channel
serial RapidIO for multiple transmission modes
[J]. Computer Engineering & Science, 2019, 41(2): 233-239.
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