Abstract: To meet the demand for controlling low-latency acceleration components, this paper proposes a multi-threaded interrupt-free RV32I microprocessor (MIRV) architecture and its associated software system. MIRV adopts a six-stage pipeline, single-issue in-order execution structure, utilizing data forwarding techniques to resolve most intra-thread data hazards. The hardware supports four-thread register files and program counters, employing a coarse-grained thread scheduling mechanism that enables zero-overhead thread switching when intra-thread data or control hazards cannot be resolved. Additionally, this paper introduces a hardware-software unified signaling mechanism, leveraging dedicated CSR (Control and Status Register) registers to facilitate thread suspension and rapid wake-up for signals from external acceleration components. Software-based signal handling is implemented to achieve multi-thread synchronization and mutual exclusion. After synthesis, MIRV occupies 1 811 LUTs and achieves a 210 MHz clock frequency. Compared to PicoRV32 and DarkRISCV, MIRV demonstrates higher ope- rating frequency and superior performance. We implemented a producer-consumer-based LED chaser control test case in C on the MK7160FA development board. In this experiment, the latency from hardware timer signal generation to software-driven external LED control signals was only 10 clock cycles, validating MIRV’s low-latency response capability to external hardware events. With low hardware resource consumption, high performance, and high-level language programmability, MIRV is well-suited as a controller for various low-latency acceleration components.

Key words: low-latency, multi-threading, interrupt-free support, RISC-V, microcontroller