Abstract: Compared to binary logic,ternary logic offers more logic states,endowing ternary logic-based circuits with advantages including smaller area,higher utilization,improved transmission efficiency,and enhanced security.This paper implements fundamental ternary logic gates using commonly available carbon nanotube field-effect transistors (CNFETs),establishes a functionally complete ternary logic library,and proposes a method to reduce switching delay by minimizing the CNFETs physical channel lengthand and source/drain length.Based on the developed ternary logic library,a 1-bit multiplier circuit was designed and implemented.HSPICE simulations verified both the circuit performance and the effectiveness of the proposed delay reduction method,demonstrating an average 47 ps reduction in switching delay compared to prior ternary 1-bit multipliers.In the actual circuit application,this paper builds the ternary logic cell library that can be used for higher order circuit synthesis and physical design of the circuit.The method to lower the ternary circuit switching delay time for the future,represented by high-performance chip microprocessor and artificial intelligence to lay a good foundation for very large-scale integration.

Key words: carbon nanotube field-effect transistor(CNFET), tenary logic, multi-valued-logic