Abstract: Chiplet technology has emerged as a promising approach to extend Moore’s Law and enhance chip performance due to its low cost, high yield, and high integration density. Currently, research on inter-chiplet transmission primarily focuses on high-speed interconnect interfaces, while the study of protocol conversion technology from the network-on-chip (NoC) to chiplet interfaces remains underexplored, posing a bottleneck for transmission latency and bandwidth between chiplets. This paper proposes a high-bandwidth and low-latency protocol conversion mechanism, named HSI. HSI employs a combined polling scheduling strategy to read multiple types of Flits from the NoC, thereby reducing transmission latency and enhancing bandwidth. It utilizes a multi-slice packet format to encapsulate Flits, improving effective bandwidth utilization, and adopts a multi-write single-read queue structure to support parallel memory access for multiple Flits, reducing parsing latency. To validate the superiority of HSI, this paper implements and verifies the HSI mechanism with respect to the mainstream CHI network protocol and UCIe chiplet interface protocol. The results demonstrate that HSI achieves a transmission bandwidth of up to 512  Gbit/s, which is compatible with the transmission bandwidth of 32-lane UCIe and the memory access bandwidth of DDR5.0. Moreover, the transmission latency for a single Flit is merely 6.05 ns, while the average transmission latency for burst Flit streams ranges from 1.2~1.7 ns.

Key words: multiple chiplets, network-on-chip(NoC), protocol transition mechanism, coherent hub interface(CHI) protocol, universal chiplet interconnect express(UCIe) protocol