Abstract:

Image matching algorithms based on the Hausdorff distance are robust enough, but they are too computationally expensive to be used in embedded systems   . Software implementations of the algorithms are hardly real-time. A robust and real-time implementation scheme of image matching using the partial Haus dorff distance measure is presented on FPGA. In order to fully utilize the hardware resources on FP（;A, it first proposes a parallel image matching alg gorithm after the parallel characteristics are analyzed. Then a corresponding architecture implemented on FPGA is introduced, which is organized as a co arse-grained pipeline containing three stages. Experimental results show that our work outperforms the related proposals. A speedup of almost 50 is achi  eved compared with the software solution on PCs （Pentium 4 2.8 GHz）.

Key words: Hausdorff distance, image matching, parallel algorithm;FPGA