Abstract:

This paper discusses the sign prediction and iterative calculation of the CORDIC algorithm in the rotation mode, and uses a parallel computation technique to accelerate it. We propose the sign prediction mechanism of subsection sign prediction and adding the correcting rotation, and use a method of un  folded subsection iteration and a three-in adder tree to perform the iterative calculation of the CORDIC algorithm. These techniques effectively reduce    the correcting rotations and the cost of hardware, and enhance the computing performance. Finally the parallel CORDIC architecture is implemented on the  FPGA chip of StratixlI from Altera.

Key words: CORDIC, sign prediction, FPGA