Leading Zero Detecting (LZD) is a quite critical step during the procedure of floatingpoint addition operation,and thus the design of a highperformance LZD algorithm is of great significance for improving the overall performance of a floatingpoint adder.In order to reach the demands of highperformance floatingpoint addition operations in 64bit CPU’s floatingpoint units,we design and implement two LZD algorithms based on FFO,and compare the  performances of them.According to the results of logic synthesis, a modified parallel LZD algorithm presented in this paper shows higher performance.Furthermore,by precalculating the amount of bytes in normalized shift operations,this algorithm can also parallelize LZD with coarsegrained byteshifting operations,which further reduces the latency in the critical path of the floatingpoint units.