The read/write channel is the electronic circuit between the readwrite head for disks and the device controller,and its main function is to write and recover data reliably.The servo signal sampling clock is an important part of servo signal detection and its design goal is to improve the servo signal transmission rate as well  as maintain the low BER,which makes strict demands on data sampling processing and clock recovery circuit design.This paper offers the servo interpolated timing recovery model based on the τ factor after analysizing the current PLL timing recovery implementation,and adopts a better solution.This paper also deduces the coefficient of interpolator,then studies the realization of the interpolator by hardware and FPGA.Through a comparison test with the linear interpolation scheme,the interpolated model can obtain better harmonic frequency.