Computer Engineering & Science >
Design and Implementation of a 3GPacketFiltering Algorithm Based on FPGA
Received date: 2009-06-25
Revised date: 2009-10-10
Online published: 2010-07-25
Based on the FPGA platform, a system is designed which captures and filters data packets in the PS of the TDSCDMA core network. And a high speed strategy ,which takes advantage of the Bloom filter and other algorithms,is proposed to filter data packets with the Hash algorithm , the strategy is implemented with Verilog. Finally,the programme downloaded to the FPGA development board is tested. When the users supervised obey the uniform distribution in a largescale way,it can process the GTP packets in a linear rate and filter the packets of the specified users.
ZHANG Xiaoxiao,HUANG Jie . Design and Implementation of a 3GPacketFiltering Algorithm Based on FPGA[J]. Computer Engineering & Science, 2010 , 32(8) : 29 -31 . DOI: 10.3969/j.issn.1007130X.2010.
/
| 〈 |
|
〉 |