Manycore CPUs prefer selecting SPM, and a noncached onchip SRAM acts  as the fast memory in these memory hierarchies owing to the area and power consumption. These memory hierarchies need software to  explicitly manage data placement and data transfer. This article proposes an easy stackanalogy onchip memory dynamic deallocation approach applied to program memoryaccesssequence optimizations with manycore memory hierarchies. It introduces an ILP solver to develop a method when the sum of the array variable sizes in each program phase is larger than the onchip memory size. The experimental results show that this approach can improve significantly the performance.