With the reduction in IC feature size and increase in integration, the soft error problem in microprocessors is becoming more and more serious. In order to improve the reliability of microprocessors, designers need to estimate the soft error rate of various components accurately for their faulttolerance design. In this paper, the estimation model for the microprocessor architectural vulnerability to soft errors is studied. Based on the model, major components’ vulnerability to soft errors in superscalar microprocessors is evaluated. The tradeoff design between reliability and performance is also discussed. The experimental results can guide microprocessors’ soft error prevention and protection, and can also provide references for the faulttolerance design of major components in microprocessors.