Computer Engineering & Science >
An I/O Restricted Parallel Speedup Model and the Scalable I/O Architecture
Revised date: 2009-04-14
Online published: 2011-03-25
The effective solutions for the I/O bottleneck can be found from the following six levels, including applications, algorithms, languages and compilers, runtime libraries, operating systems, and I/O architecture. Among all the levels mentioned above, the I/O architecture is the most fundamental. In order to meet the I/O requirements and challenges, along with our research task of a high performance parallel computing system, this paper presents a theoretical study of I/O architectures, from which we can make it possible the high performance and scalability in terms of I/O architecture level. The current parallel I/O performance analysis lacks scientific theoretical models to support the I/O architecture design. The paper studies the impact of I/O workload on the scalability of parallel computing systems and proposes an I/O restricted parallel speedup model. Based on this model, which can be used to guide I/O architecture design, a scalable parallel I/O architecture for high performance computing is presented. Moreover, the paper analyzes several strategies for improving the system scalability, which serves as the basis for further study.
LI Qiong,DU Yunfei,YANG Xuejun . An I/O Restricted Parallel Speedup Model and the Scalable I/O Architecture[J]. Computer Engineering & Science, 2011 , 33(3) : 28 -33 . DOI: 10.3969/j.issn.1007130X.2011.
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