FaultTolerance Techniques for OnBoard Parallel&nbsp; Computer System Based on Distributed Architecture

WANG Weicheng,LUO Yu

doi:10.3969/j.issn.1007130X.2011.

Computer Engineering & Science >

2011 , Vol. 33 >Issue 3: 51 - 56

DOI: https://doi.org/10.3969/j.issn.1007130X.2011.

论文

FaultTolerance Techniques for OnBoard Parallel Computer System Based on Distributed Architecture

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（School of Computer Science,National University of Defense Technology,Changsha 410073,China）

Received date: 2009-07-03

Revised date: 2009-11-05

Online published: 2011-03-25

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Abstract

Faulttolerant techniques can provide high reliability for onboard computers

running in the outer space, the current multinode onboard systems are designed as a master

slave structure, which focuses on the strategy of faulttolerance in the master node and

hereby contains a hidden danger. A parallel faulttolerant computer system with a distributed

framework is proposed in this paper. Based on the framework, the computing nodes and fault

tolerant units are designed and some novel faulttolerant strategies are introduced. Our work

can serve as an important guideline for the development of the related projects.

Key words： faulttolerance;onboard computer;distributed system

Cite this article

WANG Weicheng,LUO Yu . FaultTolerance Techniques for OnBoard Parallel Computer System Based on Distributed Architecture[J]. Computer Engineering & Science, 2011 , 33(3) : 51 -56 . DOI: 10.3969/j.issn.1007130X.2011.

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