• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊
论文

Design and Implementation of a 32Bit Unsigned Parallel Multiplier

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  • (School of Information Science and Engineering,Central South University,Changsha 410075,China)

Received date: 2008-11-21

  Revised date: 2009-02-08

  Online published: 2010-03-28

Abstract

ased on the traditional Booth 4 algorithm,we adopt the Wallace tree of a balanced 4:2 compressor to compute the sum of partial products and finally use CPA to get the final sum. It is shown that this scheme has a higher speed and a small delay than the traditional CSA array multiplier.The circuit is described using the Verilog HDL language and is synthesized by ISE9.2.

Cite this article

HU Xiaolong,YAN Xuyang . Design and Implementation of a 32Bit Unsigned Parallel Multiplier[J]. Computer Engineering & Science, 2010 , 32(4) : 122 -124 . DOI: 10.3969/j.issn.1007130X.2010.

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