关键词: 二进制翻译 动态优化 微处理器 指令集体系结构 可扩展性

Abstract:

Architects always trade off between code compatibility and architecture novelty. To keep the backward compatibility of new architectures, new innovati  on will be too difficult to apply, or even tune the result architecture with terrible complexity. This paper presents VISA, a scalable processor archite  cture based on dynamic binary translation （BT） and optimization. Keeping the full compatibility, VISA extends the design space of architecture at the  same time. Simulation shows that VISA is better than traditional BT. And it has further potential both in performance and scalability space.

Key words: （binary translation, dynamic optimization, microprocessor, instruction set architecture, scalabili , ty）