面向WCET分析的实时多核体系结构研究

J4 ›› 2014, Vol. 36 ›› Issue (03): 393-398.

面向WCET分析的实时多核体系结构研究

陈芳园1，丁亚军1,张冬松2,吴飞3,任秀江1

（1.江南计算技术研究所,江苏无锡 214083;2.中国人民解放军镇江船艇学院,江苏镇江 212000;
3.上海工程技术大学电子电气工程学院,上海 201620）

收稿日期:2013-10-12 修回日期:2013-12-20 出版日期:2014-03-25 发布日期:2014-03-25
基金资助:
国家自然科学基金资助项目(61272097)；上海市教委科研创新重点基础研究项目(12ZZ182)

Research of realtime multi-core architecture for WCET analysis

CHEN Fangyuan1，DING Yajun1，ZHANG Dongsong2，WU Fei3， REN Xiujiang1

（1.Jiangnan Institute of Computing Technology,Wuxi 214083;
2.Zhenjiang Watercraft College of PLA,Zhenjiang 212000;
3.College of Electronic and Electrical Engineering,Shanghai University of Engineering Science,Shanghai 201620,China)

Received:2013-10-12 Revised:2013-12-20 Online:2014-03-25 Published:2014-03-25

摘要/Abstract

摘要：

随着工艺技术的发展以及嵌入式实时应用范围的不断扩大和需求的不断提升，多核处理器必将凭其高性能和低功耗特性应用到嵌入式实时领域中。但是，多核处理器体系结构很难甚至无法满足实时系统的实时限制和对WCET的可预测性要求。从多核中的共享资源入手，分析多核中的片上共享资源（共享Cache、片上互连）和片外共享资源（片外存储）对WCET分析的影响，探讨了各种干扰下的WCET分析方法。介绍了两种多核WCET分析模型：多核静态WCET分析模型和多核混合WCET分析模型；同时，针对嵌入式实时应用提出了多核设计原则。

关键词: 多核体系结构, 嵌入式实时系统, 实时任务, WCET

Abstract:

With the development of technology and the increasing growth of applications and requirements in embedded realtime systems, multicore processors will be adopted in embedded realtime systems for its high performance and low power features. However, the multicore architecture is hard, even impossible to satisfy the requirement of realtime and the predictability of WCET. Starting with the shared resources, we analyze the influence of onchip shared resources and offchip resources on WCET analysis, and discuss various WCET methods. Two WCET models are introduced: multicore static WCET model and multicore hybrid WCET model. At last, the multicore design rule for the realtime application is proposed.

Key words: multi-core architecture;embedded realtime system;realtime task;WCET

陈芳园1，丁亚军1,张冬松2,吴飞3,任秀江1. 面向WCET分析的实时多核体系结构研究[J]. J4, 2014, 36(03): 393-398.

CHEN Fangyuan1，DING Yajun1，ZHANG Dongsong2，WU Fei3， REN Xiujiang1. Research of realtime multi-core architecture for WCET analysis [J]. J4, 2014, 36(03): 393-398.

参考文献

［1］International technology roadmap for semiconductors 2008 update［EB/OL］.［20080821］. http://public.itrs.net.
［2］Davis R I, Burns A. A survey of hard realtime scheduling algorithms and schedulability analysis techniques for multiprocessor systems［R］. Technical Report YCS2009443, Department of Computer Science University of York, 2009.
［3］Hirata K, Goodacre J. Arm mpcore:The streamlined and scalable arm11 processor core［C］∥Proc of Design ASPDAC’07, 2007:747748.
［4］Pham D C, Aipperspach T, Boerstler D, et al. Overview of the architecture, circuit design, and physical implementation of a firstgeneration cell processor［J］. IEEE Journal of SolidState Circuits, 2006,41(1):179196.
［5］Puschner P, Burns A. A review of worstcase executiontime analysis［J］. RealTime Systems, 2000,18(2/3):115127.
［6］Thiele L, Wilhelm R. Design for timing predictability［J］. RealTime Systems, 2004,28(2/3):157177.
［7］Li Y T S, Malik S, Wolfe A. Cache modeling for realtime software:Beyond direct mapped instruction caches［C］∥Proc of IEEE RealTime Systems Symposium, 1996:254263.
［8］Theiling H,Ferdinand C,Wilhelm R.Fast and precise WCET prediction by separated cache and path analysis ［J］. RealTime Systems, 2000,18(2/3):157179.
［9］Ramaprasad H, Mueller F. Bounding preemption delay within data cache reference patterns for realtime tasks［C］∥Proc of RealTime and Embedded Technology and Applications Symposium, 2005:7180.
［10］Staschulat J, Schliecker S, Ernst R. Scheduling analysis of realtime systems with precise modeling of cache related preemption delay［C］∥Proc of ECRTS’05, 2005:4148.
［11］Fedorova A, Seltzer M, Small C, et al. Throughputoriented scheduling on chip multithreading systems［R］. Technical Report TR1704, Cambridge:Harvard University, 2005.
［12］Anderson J H, Calandrino J M. Parallel realtime task scheduling on multicore platforms［C］∥Proc of RTSS’06, 2006:89100.
［13］Calandrino J M, Anderson J H. Cacheaware realtime scheduling on multicore platforms:Heuristics and a case study［C］∥Proc of ECRTS’08, 2008:299308.
［14］Nan Guan, Stigge M, Wang Yi, et al. Cacheaware scheduling and analysis for multicores［C］∥Proc of EMSOFT’09, 2009:245254.
［15］Paolieri M, Quinones E, Cazorla F J, et al. Hardware support for WCET analysis of hard realtime multicore systems［J］∥ACM SIGARCH Computer Architecture News, 2009,37(3):5768.
［16］Rosen J, Andrei A, Eles P, et al. Bus access optimization for predictable implementation of realtime applications on multiprocessor systemsonchip［C］∥Proc of RealTime Systems Symposium, 2007:4960.
［17］Bertozzi D, Guerri A, Milano M, et al. Communicationaware allocation and scheduling framework for streamoriented multiprocessor systemsonchip［C］∥Proc of DATE’06, 2006:38.
［18］Burger D, Goodman J R, Kgi A. Memory bandwidth limitations of future microprocessors［C］∥Proc of ISCA’96, 1996:7889.
［19］Akesson B,Goossens K,Ringhofer M.Predator:A predictable SDRAM memory controller［C］∥Proc of CODES+ISSS, 2007:251256.
［20］Wilhelm R, Grund D, Reineke J, et al. Memory hierarchies, pipelines, and buses for future architectures in timecritical embedded systems［J］. IEEE Transactions on Computeraided Design of Integrated Circuits and Systems, 2009,28(7):966978.

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