一种基于SRT-8算法的SIMD浮点除法器的设计与实现

J4 ›› 2014, Vol. 36 ›› Issue (05): 797-803.

一种基于SRT-8算法的SIMD浮点除法器的设计与实现

邓子椰，陈书明，彭元喜，雷元武

（国防科学技术大学计算机学院，湖南长沙 410073）

收稿日期:2013-07-05 修回日期:2013-11-12 出版日期:2014-05-25 发布日期:2014-05-25

Design and implementation of a SIMD
floating-point divider based on SRT-8

DENG Ziye,CHEN Shuming,PENG Yuanxi,LEI Yuanwu

(College of Computer, National University of Defense Technology,Changsha 410073,China)

Received:2013-07-05 Revised:2013-11-12 Online:2014-05-25 Published:2014-05-25

摘要/Abstract

摘要：

在科学计算、数字信号处理、通信和图像处理等应用中，除法运算是常用的基本操作之一。基于SRT8除法算法，设计一个SIMD结构的IEEE754标准浮点除法器，在同一硬件平台上能够实现双精度浮点除法和两个并行的单精度浮点除法。通过优化SRT8迭代除法结构，提出商选择和余数加法的并行处理，并采用商数字存储技术降低迭代除法的计算延时，提高频率。同时，采用复用策略减少硬件资源开销，节省面积。实验表明，在40nm工艺下，本设计综合cell面积为18601.9681 μm2，运行频率可达2.5GHz，相对传统的SRT8实现关键延迟减少了23.81%。

关键词: SRT-8, SIMD, 浮点除法器, 双精度浮点, SIMD单精度浮点

Abstract:

In the area of scientific computing, digital signal processing, communication and image processing, division is one of the widely used basic operations. Based on SRT-8 algorithm, a SIMD floating-point divider is designed,which is compatible to IEEE-754 standard.The divider supports one double precision floating point division and two parallel single precision floating point division on the same hardware platform.It reduces the iterative division calculation time delay and improves the frequency by optimizing the SRT8 iterative division structure,choosing parallel processing of quotient and residue addition,and adopting rapid storage technique. Besides,it reduces hardware resources and saves area by adopting reuse strategy.Experiments show that the synthesized cell area is 18 601.968 1μm2 and the frequency reaches up to 2.5GHz with 40nm technology library,and the latency of operation is reduced by 23.81％ in comparison to the traditional implementation based on SRT-8.

Key words: SRT-8;SIMD;floating-point division;double precision floating-point;SIMD single precision floating-point

邓子椰，陈书明，彭元喜，雷元武. 一种基于SRT-8算法的SIMD浮点除法器的设计与实现[J]. J4, 2014, 36(05): 797-803.

DENG Ziye,CHEN Shuming,PENG Yuanxi,LEI Yuanwu. Design and implementation of a SIMD
floating-point divider based on SRT-8 [J]. J4, 2014, 36(05): 797-803.

参考文献

［1］Oberman S F, Flynn M. Design issues in division and other floatingpoint operations［J］. IEEE Transactions on Computers, 1997, 46(2):154161.
［2］Oberman S F. Floatingpoint division and square root algorithms and implementation in the AMDK7 microprocessor［C］∥Proc of the 14th Symposium on Computer Arithmetic,1999:106115.
［3］NVIDIA.Fermi:NVIDIA’s next generation CUDA compute architecture［EB/OL］.［20091010］. http:∥www.nvidia.com /content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf.
［4］Sharangpani H,Arora H. Itanium processor microarchitecture［J］. IEEE Micro, 2000, 20(5):2443.
［5］Wang Xian,Ni Xiaoqiang,Xing Zuocheng.The analysis and research of floatingpoint division［C］∥Proc of the Computer Project and Craftwork, 2008:282283.(in Chinese)
［6］Baliga H, Cooray N, Gamsaragan E, et al. Improvements in the Intel Core2 Penryn processor family architecture and microarchitecture［J］. Intel Technology Journal, 2008, 12(3):179192.
［7］Burgess N, Hinds C N.Design of the ARM VFP11 divide and square root synthesisable macrocell［C］∥Proc of the 18th IEEE Symposim on Computer Arithmetic, 2007:8796.
［8］Gerwig G, Wetter H, Schwarz E M, et al. High performance floatingpoint unit with 116 bit wide divider［C］∥Proc of the 16th Symposim on Computer Arithmetic, 2003:8794.
［9］Liu Huaping. Research on highperformance arithmetic for floatingpoint division and the elementary functions［D］. Beijing:Institute of Computing Technology, Chinese Academy of Science, 2003.(in Chinese)
［10］Liu W,Nannarelli A. Power efficient division square root unit［J］. IEEE Transactions on Computers, 2012, 61(8):10591070.
［11］Harris D L, Oberman S F, Horowirtz M A. SRT division architectures and implementations［C］∥Proc of the 13th IEEE Symposium, 1997:1825.
［12］Fandrianto J. Algorithm for highspeed shared radix4 division and radix4 squareroot ［C］∥Proc of the 8th IEEE Symposium on Computer Arithmetic, 1987:7379.
［13］Wang Wenguang.Design and implementation of double precision 64bits floatingpoint division［D］. Changsha:Central South University, 2007.(in Chinese)
附中文参考文献:
［5］王县，倪晓强，邢座程．浮点除法算法的分析与研究［C］∥计算机工程与工艺，2008：282283．
［9］刘华平．高性能浮点除法及基本函数功能部件的研究［D］．北京：中国科学院计算技术研究所，2003.
［13］王文广．双精度64位浮点除法运算单元的设计与实现［D］.长沙：中南大学，2007．

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