关键词: 流水线, 并行计算, CRC16 CCITT校验, 最高时钟频率

Abstract:

For the past low efficient serial algorithm of CRC16 CCITT checksum, the reason of calculation inefficiency is studied and a generalpurpose parallel algorithm is introduced. The parallel algorithm is realized by Verilog HDL and simulated under the Quartus II. The Nios II custom instruction is used to show the performance improvement of the parallel algorithm in comparison to the serial algorithm. Finally, the basic parallel circuit is improved by means of multilevel pipeline technology and is simulated under Quartus II. The results reveal the problems of using pipeline technology to enhance the logic circuit Fmax with feedback structure, so a new method is also proposed in order to solve the problem. The simulation results show that the improved circuit with multistage pipeline can significantly increase the circuit Fmax and the computing efficiency of the CRC16 CCITT checksum is also improved.

Key words: pipelining;parallel computing;CRC16 CCITT checksum;maximum operating clock frequency