[1] |
AMDNEWS [EB/OL]. [20110628]. http://www.amdnews.cn/201 1/0628/1747_3.html.
|
[2] |
Lindholm E, Nickolls J, Oberman S, et al. Nvidia tesla:A unified graphics and computing architecture[J]. IEEE Micro, 2008, 28(2):3955.
|
[3] |
Ati radeon hd 2000/3000 series[EB/OL]. [20140606]. http://en.m.wikipedia.org/wiki/Radeon_R600.
|
[4] |
Woo J H, Sohn J H, Nam B G, et al. Mobile 3d graphics soc from algorithm to chip[M]. Singapore:John Wiley & Sons(Asia) Pte Ltd, 2010.
|
[5] |
Nam B G, Kim H, Yoo H J. A lowpower unified arithmetic unit for programmable handheld 3d graphics systems[J]. IETable 1Performance comparison of different shaders表1不同着色器的性能对比(V表示顶点着色器,F表示片段着色器)文献[14]文献[11]文献[13]文献[12]文献[15]文献[10]文献[16]本文工艺/nm1801801801801301806555功能单元VVVV+FV+FVV+FV+F数据类型FloatFloatFloatFloatFloatFloatFloatFloat核心频率/MHz100110100200166200400600顶点渲染性能/(M顶点/s)1201861205050141300600片段渲染性能/(M片段/s)---5050-400600功耗/mW231.8161157155407153248238面积/(M与非门)1.52.01.52.0-1.571.171.02Table 2Comparison of power efficiency and area efficiency表2功耗效率与面积效率对比(V表示顶点着色器,F表示片段着色器)文献[14]文献[11]文献[13]文献[12]文献[15]文献[10]文献[16]本文功耗效率(V)0.5181.1150.7640.3230.1230.9221.2092.521功耗效率(F)---0.3230.123-1.6132.521硬件效率(V)80938025-89.8256.4588.2硬件效率(F)---25--341.9588.2EE Journal of Solid State Circuits, 2009, 42(8):17671778.
|
[6] |
Kim W Y, Lee B H, Lee K Y, et al. Design of a fully programmable shader processor for low power mobile devices[C]∥Proc of IEEE TENCON, 2009:15.
|
[7] |
Woo J H, Sohn J H, Kim H, et al. A 152 mw mobile multimedia soc with fully programmable 3d graphics and mpeg4/h.264/jpeg[J]. IEEE Transactions On Very Large Scale Integration(VLSI) Systems, 2009, 17(9):12601266.
|
[8] |
Sohn J H,Park Y H,Yoon C W,et al.Low power 3d graphics processors for mobile terminals[J]. IEEE Communication Magazine, 2005,43(12):9099.
|
[9] |
Woo R. A 210 mw graphics lsi implementing full 3d pipeline with 264mtexels/s texturing for mobile multimedia applications[J]. IEEE Journal of Solid State Circuits, 2004, 39(2):358367.
|
[10] |
Nam B G, Lee J, Kim K. A 52.4 mw 3d graphics processor with 141m vertices/s vertex shader and three power domains of dynamic voltage and frequency scaling[C]∥Proc of IEEE International Solid State Circuits Conference, 2007:278279.
|
[11] |
Yu C H, Chung K, Kim D. A 186m vertices/s 161 mw floatingpoint vertex processor with optimized datapath and vertex caches[J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2009, 17(9):13691382.
|
[12] |
Sohn J H, Woo J H, Lee M W, et al. A 155 mw 50m vertices/s graphics processor with fixedpoint programmable vertex shader for mobile applications[J]. IEEE Journal of Solid State Circuits, 2006, 41(5):10811091.
|
[13] |
Yu C H, Chung K, Kim D, et al. A 120m vertices/s multithreaded vliw vertex processor for mobile multimedia applications[C]∥Proc of ISSCC, 2006:408409.
|
[14] |
Yu C H, Chung K, Kim D. An energyefficient mobile vertex processor with multithread expanded vliw architecture and vertex caches[J]. IEEE Journal of Solid State Circuits, 2007, 42(10):22572269.
|
[15] |
Kim D, Chung K, Yu C H, et al. An soc with 1.3g texels/s 3d graphics full pipeline engine for consumer applications[J]. IEEE Journal of Solid State Circuits, 2006, 41(1):7184.
|
[16] |
Sun Gangde.Design and research of unified architecture shader based on automatic threading and vliw[D]. Hangzhou:Zhejiang University, 2012. (in Chinese)
|
|
附中文参考文献:
|
|
孙纲德. 基于自动线程和超长指令的统一架构着色器的设计研究[D]. 杭州:浙江大学, 2012.
|