一种基于数字DAC校准的低失调动态比较器

J4 ›› 2016, Vol. 38 ›› Issue (04): 656-660.

一种基于数字DAC校准的低失调动态比较器

安康，李晋文，刘尧，常利平，梁斌

（国防科学技术大学计算机学院,湖南长沙 410073）

收稿日期:2015-10-11 修回日期:2015-12-21 出版日期:2016-04-25 发布日期:2016-04-25
基金资助:
国家自然科学基金（60873212）

A lowoffset dynamic comparator with
calibration based on digital DAC

AN Kang,LI Jinwen,LIU Yao,CHANG Liping,LIANG Bin

（College of Computer,National University of Defense Technology,Changsha 410073,China）

Received:2015-10-11 Revised:2015-12-21 Online:2016-04-25 Published:2016-04-25

摘要/Abstract

摘要：

提出一种基于二进制加权电容DAC阵列的比较器校准技术，并基于该技术65 nm CMOS工艺下设计实现了一款低功耗高精度动态比较器。基于版图数据的模拟仿真结果表明，在1.2 V的工作电压下，该校准技术可以将失调电压降低至0.25 mV以下，功耗为0.33 μW，功耗开销增大57%。

关键词: 失调电压, 失配, 动态比较器, 校准

Abstract:

We propose a calibration technique based on binary capacitor DAC. We also design a lowpower highprecision dynamic comparator using 65nm CMOS technology. Simulation results based on layout show that our proposal can reduce the offset less than 0.25mV under 1.2V supply. It achieves 0.33μW power dissipation, an increase of 57% in comparison with the comparators without calibration.

Key words: offset voltage;mismatch;dynamic comparator;calibration

安康，李晋文，刘尧，常利平，梁斌. 一种基于数字DAC校准的低失调动态比较器[J]. J4, 2016, 38(04): 656-660.

AN Kang,LI Jinwen,LIU Yao,CHANG Liping,LIANG Bin . A lowoffset dynamic comparator with
calibration based on digital DAC [J]. J4, 2016, 38(04): 656-660.

参考文献［8］

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