[1]Shen Ke-le, Xiang Dong. Three dimensional ICs thermal-driven test application scheme[J]. Acta Electronica Sinica,2013,41(6):1202-1206.(in Chinese)
[2]Luo Zu-ying, Han Yin-he, Zhao Guo-xing,et al. Thermal-scalable 3D parallel-heat-sinking integration methodology:Key SoC technology for large-scale parallel computing[J]. Chinese Journal of Computers,2011,34(4):717-728.(in Chinese)
[3]Jiao Ge, Li Lang, Liu Hui, et al. Test scheduling optimization algorithm for 3D stacked ICs under power constrains [J]. Instrument Technique and Sensor,2015(2):91-93.(in Chinese)
[4]Taouil M,Hamdioui S,Beenakker K,et al. Test cost analysis for 3D die-to-wafer stacking[C]∥Proc of 19th IEEE 2010 Asian Test Symposium (ATS),2010:435-441.
[5]Taouil M,Hamdioui S. On optimizing test cost for wafer-to-wafer 3D-stacked ICs[C]∥Proc of 2012 7th International Conference on the Design & Technology of Integrated Systems in Nanoscale Era (DTIS),2012:1-6.
[6]Taouil M,Hamdioui S. Stacking order impact on overall 3D die-to-wafer stacked-IC cost[C]∥Proc of 2011 IEEE 14th International Symposium on the Design and Diagnostics of Electronic Circuits & Systems (DDECS),2011:335-340.
[7]Chang Hao,Liang Hua-guo,Li Yang,et al. Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bonding[C]∥Proc of 2014 International Symposium on the VLSI Design,Automation and Test (VLSI-DAT),2014: 1-4.
[8]Agrawal M, Chakrbarty K. Test-cost modeling and optimal test-flow selection of 3D-stacked ICs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2015,34(9):1523-1536.
[9]Chang Hao,Liang Hua-guo,Jiang Cui-yun,et al. Optimization scheme for mid-bond test time on 3D-stacked ICs[J]. Acta Electronica Sinica,2015,43(2):393-398.(in Chinese)
[10]Lin Ze-yang, Lin Jian-hua. Research on subjective weight method based on blind number[J]. Computer & Digital En-gineering,2015,43(6):1073-1087.(in Chinese)
[11]Chih-Yao Hsu,Chun-Yi Kuo. 3D IC test scheduling using simulated annealing[C]∥Proc of 2012 International Symposium on VLSI Design,Automation,and Test (VLSI-DAT),2012:1-4.
附中文参考文献:
[1]神克乐,向东. 基于三维芯片热驱动的扫描测试策略[J]. 电子学报,2013,41(6):1202-1206.
[2]骆祖莹,韩银和,赵国兴,等. 可热扩展的三维并行散热集成方法:用于大规模并行计算的片上系统关键技术[J]. 计算机学报,2011,34(4):717-728.
[3]焦铬,李浪,刘辉,等.功耗约束下的3D_SICs测试调度优化算法[J].仪表技术与传感器,2015(2):91-93.
[9]常郝,梁华国,蒋翠云,等.一种3D堆叠集成电路中间绑定测试时间优化方案[J].电子学报,2015,43(2):393-398.
[10]林泽阳,林建华.一种基于盲数的主观赋权法研究[J].计算机与数字工程,2015,43(6):1073-1087. |